aarch64: Add Support for F16F32DOT intrinsics
Adds new advsimd intrinsics for half-precision to single-precision floating-point dot product operations on aarch64.
This commit introduces support for several new advsimd intrinsics on the aarch64 architecture, specifically for performing dot product operations between half-precision (F16) and single-precision (F32) floating-point numbers. These intrinsics enable more efficient vectorized computations involving mixed-precision floating-point data, which can be crucial for performance in graphics and machine learning workloads.
In Details
Adds new advsimd intrinsics to GCC for aarch64, targeting the F16F32DOT instruction set extension. This involves updating C++ headers, definition files, machine description patterns, and documentation to enable the use of these SIMD instructions via intrinsics, particularly for dot product operations between FP16 and FP32 formats.
- advsimd
- Advanced Single Instruction Multiple Data (SIMD) is an extension of the ARM architecture providing wide registers and vector processing capabilities for multimedia and signal processing.
- intrinsics
- Special functions that map directly to hardware instructions, allowing C/C++ code to leverage specific CPU capabilities like SIMD operations.
- F16F32DOT
- A specific instruction set extension for ARM's Advanced SIMD (AdvSIMD) that supports dot product operations between 16-bit floating-point (half-precision) and 32-bit floating-point (single-precision) numbers.