Fix or1k conditional move generation and SR_F register usage
or1k: Correctly handles conditional moves and SR_F register use, fixing compiler errors.
This commit resolves compiler errors on the or1k target related to the SR_F (status register flag) being incorrectly referenced in SImode. It reverts changes that allowed this usage and adjusts the conditional move (cmov) optimization logic to ensure correct code generation, even when TARGET_CMOV is not explicitly enabled. A new test case is added to cover the fix.
In Details
Reverts the relaxation of or1k_hard_regno_mode_ok and or1k_can_change_mode_class to prevent SImode access to FLAG_REGS (SR_F), addressing PR target/126081. It modifies or1k_noce_conversion_profitable_p to correctly handle cmov expansion by always checking or1k_is_cmov_insn. This ensures that cmov instructions are lowered appropriately even if TARGET_CMOV is not set, relying on later split passes to handle the instruction selection.
- or1k
- An open-source RISC processor core architecture. GCC support for this architecture is being updated.
- SR_F
- Likely refers to the Floating-point Status and Control Register flag in the or1k architecture, used for conditional operations.
- SImode
- A mode in GCC's internal representation (RTL) representing a single signed integer, typically 32 bits.
- RTL
- Register Transfer Language, an intermediate representation used by GCC between the front-end and the back-end. It represents operations on registers.
- cmov
- Conditional move instruction. It moves a value from a source to a destination only if a specified condition is met.
- PR126081
- A Problem Report identifier for a bug filed against the GCC bug tracking system, indicating an issue specific to the or1k target.