i386: Avoid XCHGB %rH, %rL in bswaphi2 on non-Pentium4
Avoids high-latency XCHGB instruction for bswaphi2 on targets other than Pentium 4.
For i386 targets prior to Pentium 4, the XCHGB %rH, %rL instruction has higher latency than ROLW. This commit changes the instruction selection for the bswaphi2 (byte swap for half-word) and related patterns to avoid XCHGB. It utilizes the enabled attribute to hard-disable the unwanted XCHGB alternatives, replacing the previous use of preferred_for_size and preferred_for_speed attributes.
In Details
Revises instruction selection for bswaphi2 on i386 to avoid the XCHGB instruction when targeting pre-Pentium 4 CPUs. Benchmarking revealed XCHGB has higher latency than ROLW on these older microarchitectures. The change replaces the preferred_for_size/preferred_for_speed attributes with a hard enabled attribute to disable XCHGB for *bswaphi2_movbe, *bswaphi2, and *bswaphisi2_lowpart, forcing the use of more performant alternatives.
- i386
- The original 32-bit Intel x86 architecture, and by extension often used to refer to compatible architectures.
- XCHGB
- An x86 assembly instruction that exchanges the contents of two byte registers.
- bswaphi2
- An internal GCC pattern name representing the instruction for swapping the byte order of a 16-bit half-word.
- Pentium 4
- A series of Intel microprocessors based on the NetBurst microarchitecture, released in 2000.
- latency
- In processor terms, the time delay between the initiation of an operation and the availability of its result.
- ROLW
- Rotate Left Word, an x86 instruction that rotates the bits of a 16-bit register.
- attribute
- Compiler directives that provide additional information about program elements, often used in internal definitions to guide optimization or instruction selection.