RISC-V excludes t1 from sibcall registers to prevent overwrites
RISC-V's t1 register is now excluded from sibcall register sets to prevent overwrites by RVV epilogues, ensuring correct indirect sibcall execution.
The t1 register on RISC-V has been excluded from the SIBCALL_REGS set and mapped to JALR_REGS. This change prevents an indirect sibcall target stored in t1 from being overwritten by the RVV (RISC-V Vector) scalable-frame epilogue before the final jump. Test cases are updated to reflect this register class change.
In Details
To prevent an indirect sibcall target in t1 from being overwritten by an RVV scalable-frame epilogue prior to the final jump, t1 is now mapped to JALR_REGS instead of SIBCALL_REGS. The REG_CLASS_CONTENTS in riscv.h and riscv_regno_to_class in riscv.cc are updated accordingly. Test cases related to pr97682 and RVV features are adjusted.
- SIBCALL_REGS
- A defined set of registers on the RISC-V architecture that are reserved or recommended for use during sibling calls (sibcalls).
- t1 register
- A specific temporary register (x1) within the RISC-V architecture, often used for various purposes including function calls and temporary storage.
- RVV
- RISC-V Vector extension, a set of instructions for high-performance vectorized computations.
- scalable-frame epilogue
- Code executed at the end of a function call on systems using RVV, which dynamically adjusts the stack frame size based on vector register usage.
- JALR_REGS
- Registers on the RISC-V architecture that are generally suitable for use with the Jump And Link Register (JALR) instruction, often used for indirect jumps and returns.