RISC-V: Allow vector register overlap for vfwcvt.x[u].f.v.
RISC-V vector conversion instructions now support register overlap.
This change enables register group overlap for the RISC-V vector instructions vfwcvt.x.f.v and vfwcvt.xu.f.v. Similar to the existing support for v[sz]ext.vf8, this allows the destination register group to overlap with the source register group. This modification is implemented by leveraging the Wvr constraint in the vector.md configuration, facilitating more flexible and potentially efficient register allocation for these conversion operations.
In Details
The RISC-V vector (RVV) backend now permits register group overlap for the vfwcvt.x.f.v and vfwcvt.xu.f.v instructions, extending a capability previously available for v[sz]ext.vf8. This is achieved by updating config/riscv/vector.md to utilize the Wvr constraint. Allowing overlap can enable more efficient code generation by reducing register pressure and instruction count in scenarios where source and destination registers can be shared, potentially improving performance.
- vfwcvt.x.f.v
- A RISC-V vector instruction that converts floating-point values to signed integer values within a vector register.
- vfwcvt.xu.f.v
- A RISC-V vector instruction that converts unsigned integer values to floating-point values within a vector register.
- Register group overlap
- A situation in vector processing where the destination registers for an instruction may partially or fully overlap with the source registers, requiring careful management to avoid corrupting data before it's used.
- vector.md
- A machine description file used by GCC to define how vector operations are mapped to specific CPU instructions.
- Wvr constraint
- A specific constraint used in GCC's machine description files to indicate that a register operand can be shared between the source and destination of certain vector operations.