aarch64: Fold merging svextb/svexth/svextw with a ptrue to AND [PR120027]
Optimizes SVE extension instructions with all-true predicates to simple AND operations.
This commit optimizes SVE (Scalable Vector Extension) instructions that perform byte, halfword, or word extensions (svextb, svexth, svextw) when used with an all-true predicate (svptrue_b64) in their merging form. Previously, these instructions would generate unnecessary predicated operations. The compiler now folds these specific cases into a single, unpredicated bitwise AND operation, simplifying the generated code and improving performance for unsigned types.
In Details
This patch adds a fold method to svext_bhw_impl in config/aarch64/aarch64-sve-builtins-base.cc to handle a specific SVE optimization. For unsigned types, svextb/h/w intrinsics with the merging (_m) form and an all-true predicate (svptrue_b64) are recognized. These are equivalent to a zero-extension, which can be represented by a BIT_AND_EXPR with a mask, rather than the more complex predicated UXT instruction. This optimization targets PR120027 and generates simpler, more efficient code when the predicate doesn't selectively mask elements.
- SVE
- Scalable Vector Extension. An ARM instruction set architecture extension that provides a flexible, highly parallel processing capability for computationally intensive workloads, adapting to different vector lengths.
- svextb/svexth/svextw
- SVE intrinsics that perform byte (
_b), halfword (_h), or word (_w) extend operations on vector registers. They are used for operations like zero-extension or sign-extension. - Predicate
- In vector processing, a predicate is a control mechanism that determines which elements within a vector register are affected by an operation. An all-true predicate (
svptrue_b64) means all elements are affected, effectively disabling conditional behavior for that operation. - Merging Form (_m)
- A mode for SVE operations where the inactive elements of the destination vector are preserved from their previous values, while active elements are updated according to the operation. This contrasts with other forms like
_z(zeroing) or_x(updating based on input). - BIT_AND_EXPR
- GCC's internal representation for a bitwise AND operation between two expressions. This is a GIMPLE or TREE-level construct used during optimization.