RISC-V: Add minimal Ziccid extension support
GCC compiler gains minimal support for the RISC-V Ziccid extension.
This commit adds minimal support for the RISC-V Ziccid extension, which deals with instruction and data coherence and consistency, depending on Ziccif. The changes include updates to the extension definitions, options, documentation, and the addition of new test cases.
In Details
The integration of the RISC-V Ziccid extension into GCC requires updates to \riscv-ext.def\, \riscv-ext.opt\, and \doc/riscv-ext.texi\. Ziccid addresses instruction and data cache coherence and consistency issues, which are critical for multiprocessor systems and high-performance computing to ensure correct memory ordering and visibility. By recognizing Ziccid, GCC can generate code that correctly leverages these coherence mechanisms, preventing subtle bugs in complex parallel execution environments. New tests verify its functionality.
- RISC-V Ziccid
- The RISC-V Ziccid extension provides mechanisms to ensure instruction and data coherence and consistency across multiple processor cores and memory system components. This is vital for correct operation in multi-core systems and systems with complex memory hierarchies.
- Ziccif
- Ziccif is likely a prerequisite RISC-V extension that provides baseline co nce features, upon which Ziccid builds. It may define fundamental cache coherence protocols or interfaces that Ziccid requires for its more advanced functionality.
- cache coherence
- Cache coherence ensures that all processors in a multi-processor system have a consistent view of memory, even when caches are involved. It prevents stale data from being used by different cores.