SH: Avoid FPUL for fp-constant loads
Optimizes floating-point constant loads on SH by avoiding unnecessary use of FPUL register.
This commit optimizes floating-point constant loads on the SH architecture by adjusting instruction patterns. Specifically, it changes the constraint for a constant-pool load from FPUL-specific to a more general one, discouraging FPUL usage for regular floating-point registers while still allowing it when necessary. This change aims to improve performance by preferring dedicated floating-point registers.
In Details
For SH, the movsf_ie instruction pattern's FPUL alternative for constant-pool loads is marked with a more general *y constraint, encouraging IRA to cost it as FP_REGS rather than FPUL. LRA still accepts the FPUL variant as a more expensive option. This aims to reduce incidental use of the FPUL register for loads that could use the standard FPU registers.
- FPUL
- On SH architectures, this refers to a specific register or set of registers used for floating-point operations. This commit distinguishes between using FPUL for general floating-point operations and when it's specifically required for certain instructions.
- IRA
- Instruction Register Allocation, a phase in GCC's backend that assigns physical registers to virtual registers. IRA aims to minimize register pressure and spilling.
- LRA
- Last Register Assignment, an earlier register allocation scheme in GCC. While largely superseded by IRA, some paths or specific architectures might retain elements or transition logic.
- constant pool
- A data section in an executable or object file where constant values (like literal numbers or strings) are stored. They are loaded into registers at runtime.