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JULY 29, 2026
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risc-v Performance Win

RISC-V uses pseudo-register for sibcall addresses

RISC-V compiler now uses a pseudo-register for sibcall addresses to improve optimization and avoid unnecessary reloads.

The RISC-V compiler has been modified to use a pseudo-register for materializing sibcall addresses. This change allows the register allocator (LRA) to directly select registers suitable for sibcalls, preventing a potential reload of a temporary register (t1) that is needed for normal calls. This is an optimization that ensures sibcalls are handled correctly without interference.

In Details

To prevent LRA from reloading a sibcall address materialized in t1 (which is excluded from SIBCALL_REGS), this change introduces a pseudo-register for sibcall address materialization. The riscv_legitimize_call_address function is updated to accept a sibcall parameter, and the riscv.md file is adjusted to use this pseudo for sibcalls, ensuring t1 remains available for normal calls. This is an optimization, not a bug fix.

For Context
sibcall
A subroutine call that uses a stack-indirect jump instruction, often used for optimizing small function calls and calls through function pointers.
pseudo-register
A temporary, virtual register used by the compiler during optimization passes before final register allocation.
LRA
Local Register Allocation, a phase in the compiler's backend that assigns physical machine registers to program variables and temporaries.
SIBCALL_REGS
A set of registers designated by the RISC-V architecture specifically for use in sibcall operations.
constraint
A specification in assembly code or compiler directives that dictates which type of register or operand should be used for a particular operation.
Filed Under: risc-voptimizationregister-allocation