RISC-V: Improve costing for if-converted sequences
Adjusts RISC-V cstore instruction costing to better handle if-conversion and reduce unnecessary instructions.
This patch refines the cost model for RISC-V compare-and-store (cstore) operations, addressing suboptimal patterns that often lead to additional subregister copies, zero extensions, and move instructions. By modifying the cost routines, the compiler aims to improve the efficiency of sequences involving these operations, particularly when they are part of if-converted code. This change helps avoid missed optimization opportunities and reduces the generation of suboptimal instruction sequences.
In Details
The RISC-V backend's cstore instruction expander currently uses a fixed SI (single integer) destination register. This limitation forces the generation of redundant instructions like subregister copies and zero extensions when inputs have different modes, especially during sequences involving SCC (Set Condition) instructions. This commit modifies the cost logic to better account for these intermediate instructions that participate in if-conversion. The goal is to prevent the cost model from incorrectly favoring generalized conditional moves over potentially more efficient conditional store…
- if-conversion
- A compiler optimization technique that transforms conditional control flow (like if-else statements) into conditional move or select instructions. This can help expose more Instruction-Level Parallelism (ILP) by linearizing code, but it can also increase code size and complexity if not costed carefully.
- cstore
- Compare-and-store instruction. On RISC-V, this typically involves conditionally storing a value based on some comparison, often used in the context of atomics or conditional updates.
- SI destination
- SI likely refers to a 'Single Integer' register destination in the RISC-V architecture's register set. In this context, it means the cstore instruction's output is always written to a specific type of register, regardless of the input operand's type or mode.
- subreg copies
- Operations to copy data between a sub-register and a larger register. This is often generated by compilers when a smaller data type (e.g., a 16-bit integer) is used in an operation that typically handles larger registers (e.g., 32-bit or 64-bit), requiring the smaller value to be sign/zero-extended and potentially copied.