WEDNESDAY, JULY 8, 2026
risc-v
RISC-V: Enable TARGET_SFB_ALU for andes-45-series CPUs
Enables short forward branch ALU support for a specific RISC-V CPU series.
This commit enables the TARGET_SFB_ALU option for the andes-45-series RISC-V tune. This change aligns the compiler’s scheduling reservations with the existing capabilities of the andes-45-series, ensuring more accurate code generation for this CPU.
In Details
Enables the TARGET_SFB_ALU scheduling reservation for the RISC-V andes-45-series tune. This corrects a mismatch between the hardware's capabilities, as reflected in the .md file, and the compiler's internal configuration, potentially improving instruction scheduling for this specific processor.