RISC-V: Enable register overlap for vfwcvt.f.f.v vector instruction.
RISC-V backend now allows register overlap for the vfwcvt.f.f.v vector instruction.
This commit updates the RISC-V backend to permit register overlap for the vfwcvt.f.f.v vector instruction. Similar to how vsext.vf8 and overlay.vf8 handle register reuse, this change allows the compiler to more efficiently schedule vector operations. By leveraging the Wvr constraint in the machine description, the backend can now better utilize available registers when generating code for this specific widen-converting floating-point vector instruction.
In Details
The RISC-V vector backend's machine description (config/riscv/vector.md) is updated to allow register overlap for the vfwcvt.f.f.v instruction. This is achieved by leveraging the Wvr constraint, which signifies that the destination register in a vfwcvt.f.f.v operation can overlap with source registers used in subsequent operations, similar to the handling of vsext.vf8. This permits more aggressive register allocation and instruction scheduling.
- RISC-V Vector (RVV)
- A set of extensions for the RISC-V instruction set architecture designed to accelerate vector and SIMD processing through wide registers and specialized instructions.
- vfwcvt.f.f.v
- A RISC-V Vector instruction that performs a widening conversion from a lower-precision floating-point format to a higher-precision floating-point format within vector registers.
- register overlap
- A situation where the compiler or hardware allows the destination register of an instruction to be the same as, or overlap with, a source register used by a subsequent instruction, enabling more efficient register usage.
- Wvr constraint
- A machine-dependent constraint in GCC's RTL (Register Transfer Language) that likely indicates a specific set of registers or register usage patterns allowed for vector operations on RISC-V, particularly concerning register overlap.