Improve AND synthesis
Enhances RISC-V AND instruction synthesis using integer cost heuristics and rotation operations.
This commit improves the synthesis of AND operations for RISC-V architectures by changing the cost heuristic from riscv_const_insns to riscv_integer_cost, aligning it with similar optimizations for XOR and OR operations. Additionally, it introduces a new optimization that utilizes rotation instructions combined with bit clearing for constants with sparse set bits, improving code generation for cases like x & 0xff000000000000ff.
In Details
The RISC-V backend's AND synthesis has been updated. It now uses riscv_integer_cost instead of riscv_const_insns for evaluating constants, mirroring optimizations in IOR/XOR. Furthermore, a new technique is introduced to handle AND operations with constants that have sparse set bits, such as 0xff000000000000ff. This involves rotating the input operand, clearing the unwanted bits using zext.h (or zext.w and andi), and then rotating back, resulting in more efficient instruction sequences like rori + zext.h + rori.
- RISC-V
- An open-standard instruction set architecture (ISA) based on reduced instruction set computing principles, popular for embedded systems and custom accelerators.
- AND synthesis
- The process within the compiler's code generation phase where high-level bitwise AND operations are translated into specific machine instructions.
- riscv_integer_cost
- A cost model or heuristic used in the RISC-V GCC backend to evaluate the efficiency of generating different instruction sequences for integer operations.
- riscv_const_insns
- Likely refers to a previous or alternative cost model in the RISC-V GCC backend that specifically evaluated sequences involving immediate constants.
- rotation instructions (`rori`)
- Instructions that shift bits within a register and wrap the shifted bits around to the other end, useful for rearranging bit patterns.
- zext.h
- Zero-extend halfword. A RISC-V instruction that takes a 16-bit value, zero-extends it to the register width (e.g., 64-bit), and stores it.