Improve x86 horizontal FP instruction costing.
Fixes x86 combine optimization for horizontal FP add/sub instructions.
This commit refines the instruction costing for x86’s horizontal floating-point add and subtract operations, specifically for SSE3 and AVX instructions. By introducing a new cost_special attribute and correctly costing these hadd/hsub operations, the combine optimization pass can now properly identify and recover the single hadd instruction in certain reduction patterns. This addresses issues in test cases previously failing due to incorrect cost estimations.
In Details
This patch improves how GCC costs certain x86 SSE3/AVX horizontal floating-point instructions (haddv2df3, hsubv2df3, etc.) by introducing a cost_special attribute. This attribute, set to haddsub, allows ix86_insn_cost to assign a cost similar to a standard ADD instruction. This fixes a hole in the cost model that previously prevented combine from optimizing certain horizontal reduction patterns, such as those found in pr54400.c.
- x86
- A family of instruction set architectures developed by Intel, widely used in desktop and server computers.
- SSE3
- Streaming SIMD Extensions 3, an instruction set extension for x86 processors that added several floating-point and integer processing instructions.
- AVX
- Advanced Vector Extensions, an instruction set extension for x86 processors that expanded the width of SIMD registers and introduced new instructions.
- insn_cost
- A mechanism within the compiler to estimate the execution cost (e.g., cycles) of a specific machine instruction on the target architecture.
- combine
- A GCC optimization pass that performs instruction combination and simplification, aiming to replace sequences of instructions with equivalent, more efficient ones.
- horizontal FP add/sub
- Floating-point addition or subtraction operations that combine elements from different lanes of a SIMD vector, as opposed to element-wise operations.