Disable AMX-TF32 for Diamond Rapids processors

AMX-TF32 support is disabled for Diamond Rapids CPUs in GCC.

By Haochen Jiang July 1, 2026 committed

GCC now disables AMX-TF32 support for processors codenamed ‘Diamond Rapids’. This change aligns with the Instruction Set Extension (ISE) documentation, which indicates that AMX-TF32 will not be present in these future processors. This prevents the compiler from generating code that targets an unavailable feature.

In Details

The PTA_DIAMONDRAPIDS macro in GCC's i386 configuration is updated to remove the PTA_AMX_TF32 flag. This ensures that the compiler respects the absence of the AMX-TF32 feature on upcoming 'Diamond Rapids' processors, preventing potential runtime issues or incorrect code generation.

For Context

Diamond Rapids: A codename for a generation of Intel processors. The specific features, including instruction set support, are detailed in Intel's documentation.
PTA_AMX_TF32: A flag within GCC's i386 target architecture configuration that indicates support for the AMX-TF32 instruction set.

Filed Under: i386cpuarchitecturedisable

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