RISC-V ADD synthesis exploits new instructions and costs.
RISC-V compiler can now synthesize ADD instructions more efficiently using new patterns and cost models.
GCC’s RISC-V backend gains improved ADD instruction synthesis. It now leverages the add.uw instruction for specific constant patterns and recognizes INT_MIN additions as a binvi operation. This change also refactors the cost model to use riscv_integer_cost over riscv_const_insns, enabling better selection of cheaper instructions when multiple options exist.
In Details
RISC-V instruction selection for ADD instructions. Exploits add.uw for constants with zero upper 32 bits and sign bit set. Recognizes INT_MIN + X as binvi(X) followed by add (which Combine folds). Replaces riscv_const_insns cost model with riscv_integer_cost for proper cost comparison.
Fixes xfail for xor-synthesis-2.c.
- add.uw
- A RISC-V instruction that performs an unsigned addition with a zero-extended 32-bit immediate.
- binvi
- A RISC-V instruction that performs a bitwise inversion with a zero-extended 32-bit immediate. It can be used to implement the addition of INT_MIN by flipping the sign bit.
- RISC-V instruction synthesis
- The process by which the compiler generates machine instructions from intermediate representations, aiming for efficiency and correctness for the target architecture.
- riscv_integer_cost
- A cost function used in the RISC-V GCC backend to estimate the performance cost of generating integer instructions.
- riscv_const_insns
- An older cost function that clamped instruction costs, potentially leading to suboptimal instruction selection.