AArch64 SVE now combines AdvSIMD and SVE vector duplicates.
GCC now combines AdvSIMD and SVE vector duplicates into a single instruction for AArch64, improving code generation.
The compiler previously used an intermediate 128-bit AdvSIMD register when duplicating a 64-bit or narrower value into an SVE register. This change adds a pattern that combine can use to merge two vec_duplicate instructions (scalar -> AdvSIMD and AdvSIMD -> SVE) into a single one (scalar -> SVE). This results in more efficient code generation, reducing the number of instructions needed.
In Details
This commit adds a new pattern aarch64_vec_duplicate_subvector<vconsv><vconq><mode> to aarch64-sve.md that combines scalar to AdvSIMD and AdvSIMD to SVE vec_duplicate instructions into a single scalar to SVE instruction. The VCONSV mode attribute is also added to iterators.md. This optimization avoids unnecessary intermediate registers, streamlining code generation for SVE.
For Context
AdvSIMD and SVE are vector instruction sets for AArch64 processors, allowing operations on multiple data elements simultaneously. This commit optimizes the process of duplicating scalar values into SVE registers. By directly moving scalar values to SVE registers, it reduces overhead and improves performance, resulting in faster execution of vectorized code.