x86: Disable 16-bit immediate stores when TARGET_LCP_STALL is enabled
Avoid 16-bit immediate integer store when TARGET_LCP_STALL is enabled.
This commit disables 16-bit immediate integer stores when TARGET_LCP_STALL is enabled in GCC’s x86 backend. The change avoids performance stalls on certain x86 processors. By updating the V_16_32_64:*mov<mode>_imm pattern, the compiler now avoids generating 16-bit immediate stores when TARGET_LCP_STALL is active, potentially improving performance on affected CPUs.
In Details
The mmx.md file defines instruction patterns for the x86 MMX instruction set. V_16_32_64:*mov<mode>_imm is a pattern that matches move instructions with immediate operands of 16, 32, or 64 bits. When TARGET_LCP_STALL is enabled, 16-bit immediate stores can cause performance stalls. This commit modifies the pattern to avoid these stores when the target architecture has this characteristic. The interaction with MMX is not direct; the stall applies to general-purpose code as well when the target is configured with TARGET_LCP_STALL.
For Context
When compiling code for x86 processors, the compiler chooses specific machine instructions to perform operations like moving data. Some instructions, while functionally equivalent, can have different performance characteristics on certain CPUs. This commit addresses a specific case where storing a 16-bit value directly into memory (an "immediate store") can cause a delay or "stall" on some x86 processors. The TARGET_LCP_STALL flag indicates that the target CPU has this behaviour; the compiler now avoids generating these instructions when that flag is set. This ensures better performance on those CPUs by using alternative instruction sequences.