Improve SI->DI zero/sign extension patterns for RISC-V
Improves code generation for zero-extension on RISC-V by using shift pairs when Zba/Zbb extensions are unavailable.
This patch enhances zero-extension code generation for RISC-V, particularly when the Zba/Zbb extensions are not available. It generates shift pairs for REG operands instead of relying solely on define_insn_and_split, which is now used only for MEM sources. This change leads to better code in some cases and paves the way for further optimization improvements.
In Details
This commit modifies the RISC-V backend's handling of SI->DI zero extensions. The changes primarily affect the named expanders and a closely related combiner pattern. When the Zba/Zbb extensions are not available, shift pairs are generated for REG operands. The existing define_insn_and_split is converted to define_insn that handles MEM sources only. The combinatorial pattern is simplified to a define_split.
For Context
When compiling code for RISC-V, GCC needs to handle different data types and their extensions. Zero-extension is the process of expanding a smaller data type (e.g., 32-bit integer) to a larger one (e.g., 64-bit integer) by filling the extra bits with zeros. RISC-V has optional extensions (Zba/Zbb) that provide specific instructions for this. This commit improves code generation for zero-extension when those extensions are not available, resulting in potentially faster code.