RISC-V: Add test for vec_duplicate + vmsle.vv combine with GR2VR cost 0, 1 and 15
Added new tests with assembly checks for RISC-V vectorization combining vec_duplicate and vmsle.vv into vmsle.vx, covering various GR2VR costs.
This commit adds new tests for RISC-V vectorization, specifically focusing on the combination of vec_duplicate and vmsle.vv instructions into a single vmsle.vx instruction. The tests include assembly checks to verify the correct code generation. The tests cover different costs associated with moving data from general-purpose registers to vector registers (GR2VR), which influences the compiler’s decision to perform this optimization. This ensures that the combination works as expected across a range of scenarios.
In Details
This commit adds tests to gcc.target/riscv/rvv/autovec/vx_vf/ to verify the combination of vec_duplicate and vmsle.vv into vmsle.vx based on the cost of GR2VR. The tests cover GR2VR costs of 0, 1, and 15. The vmsle.vx instruction is a vector masked set less than or equal instruction, where one operand is a vector register and the other is a scalar register.
For Context
Vectorization is a compiler optimization technique that allows performing the same operation on multiple data elements simultaneously using vector instructions. RISC-V is a modern instruction set architecture that includes vector extensions (RVV). The specific instructions being tested are related masked vector set less than or equal (vmsle) and vector duplicate (vec_duplicate). The cost of moving data between different types of registers can affect optimization decisions. This commit adds tests to ensure the compiler correctly combines these instructions under different cost constraints for moving data into vector registers.