AArch64: Add zeroing forms for predicated SVE int-/FP-to-FP conversions
The compiler now supports zeroing predication for SVE integer/FP-to-FP conversion instructions under SVE2.2 or SME2.2 when the merge operand is a constant zero…
The compiler now supports zeroing predication for SVE integer/FP-to-FP conversion instructions under SVE2.2 or SME2.2 when the merge operand is a constant zero vector. A new alternative is added to the patterns to emit a single zeroing-predication version of an instruction when the merge operand is a constant zero vector and the sve2p2_or_sme2p2 condition holds.
In Details
SVE2.2 and SME2.2 add zeroing predication to FP conversion instructions like SCVTF, UCVTF, FCVT, BFCVT, and FCVTX. This commit adds an alternative to the existing patterns in aarch64-sve.md and aarch64-sve2.md to emit the zeroing versions when the merge operand is a constant zero vector and sve2p2_or_sme2p2 is true.
For Context
The Scalable Vector Extension (SVE) is an Arm architecture extension that allows vector instructions to operate on vectors of varying lengths. Predication is a feature that allows vector instructions to be conditionally executed based on a predicate vector. Zeroing predication is a form of predication where inactive lanes in the destination vector are set to zero. This commit adds support for zeroing predication to several SVE integer/FP-to-FP conversion instructions, enabled under SVE2.2 or SME2.2, when the merge operand is a constant zero vector.