OpenRISC fixes 64-bit shift operations in GCC
GCC for OpenRISC now correctly handles 64-bit shift operations by defining `SHIFT_COUNT_TRUNCATED` and correcting shift amount predicates.
This commit resolves long-standing issues with 64-bit shift operations on the OpenRISC architecture within GCC. The fix involves defining SHIFT_COUNT_TRUNCATED to signal that shift amounts are limited to the low 5 bits, as expected by the hardware. Additionally, the predicate for 32-bit shift immediate operands was corrected from six to five bits, ensuring proper code generation for all shift instructions.
In Details
Prior to this fix, the OpenRISC GCC backend incorrectly assumed that shift counts could utilize more bits than the hardware actually supports. The OpenRISC architecture only uses the low 5 bits for both register and immediate shift amounts. This commit defines the SHIFT_COUNT_TRUNCATED macro in or1k.h to inform the RTL backend of this truncation. Furthermore, the predicates.md file was updated to introduce reg_or_u5_operand and remove reg_or_u6_operand, reflecting that immediate shift amounts for 32-bit shifts are 5-bit unsigned values, not 6-bit, thereby correcting patterns like `r…
For Context
When a computer shifts bits (moving them left or right, effectively multiplying or dividing by powers of two), it needs to know how many positions to shift. On the OpenRISC processor, there's a specific rule: whether you're shifting by a number stored in a register or by a fixed number in the instruction itself, only the last 5 bits of that number are actually used. If the compiler tries to use more than 5 bits, the shift operation won't work as expected. This change tells the GCC compiler about this 5-bit limit, fixing bugs in how it generates code for 64-bit shift operations and ensuring that programs using these shifts on OpenRISC will now behave correctly.