Improve equality comparisons of a logical AND expressions
GCC on RISC-V now optimizes equality comparisons of logical AND results, potentially reducing code size and improving instruction scheduling.
GCC’s RISC-V backend now optimizes equality comparisons where the result of a logical AND operation is compared against zero. By right-shifting trailing zeros from constant, GCC can generate more efficient code sequences. This optimization reduces data dependencies and instruction count, especially when one operand of the AND requires synthesis, leading to performance gains and code density improvements.
In Details
This patch addresses PR rtl-optimization/56096 by adding new patterns to riscv.md to optimize comparisons of logical AND operations against zero. The optimization involves right-shifting trailing zeros from the constant operand and shifting the other input accordingly. This can improve code generation when the shifted constant doesn't require synthesis and enables better instruction scheduling and reduced data dependencies, thus enabling czero.eqz.
For Context
When compiling code for RISC-V processors, GCC aims to produce the most efficient machine code possible. This commit focuses on optimizing specific code patterns that involve logical AND operations and equality comparisons. Specifically, when the result of a logical AND is compared to zero, the compiler can sometimes rewrite the code to use fewer instructions or to eliminate dependencies between instructions. Removing dependencies can allows the processor to execute instructions in parallel, speeding up the overall execution of the program.