RISC-V: Scale vector operation costs by LMUL for latency and register pressure.
The RISC-V backend now accounts for the increased cost of larger LMULs in vector operations, which should improve code generation.
This patch introduces multiplicative cost scaling (x2/x4/x8) to better model the increased latency and register pressure associated with larger LMULs (Lane Multiplier) in RISC-V vector operations. The scaling is applied uniformly in the adjust_stmt_cost function for all vector statements. This change intends to improve the accuracy of cost modeling and thus enable better optimization decisions during code generation.
In Details
This change introduces get_lmul_cost_scaling in riscv-vector-costs.cc, which is then used in costs::adjust_stmt_cost to apply LMUL scaling uniformly to all vector statements. Search snippets should explain what LMUL is in the context of RISC-V vector extensions, as well as pointing to the cost model used by GCC.
For Context
Vector extensions allow processors to perform the same operation on multiple data elements simultaneously. The RISC-V vector extension uses a Lane Multiplier (LMUL) to configure the size of these vector operations; larger LMULs increase the amount of data processed in parallel but also increase register pressure and latency. The compiler's cost model estimates the resources required for different operations, and this change updates that model for RISC-V to account for the trade-offs introduced by LMUL when auto-vectorizing code.