RISC-V: Combine vec_duplicate + vmsgt.vv to vmsgt.vx
The compiler now combines `vec_duplicate` with `vmsgt.vv` into `vmsgt.vx` on RISC-V when the cost of GR2VR is zero.
The RISC-V backend now combines vec_duplicate followed by vmsgt.vv instructions into a single vmsgt.vx instruction when the cost of transferring data from a general-purpose register to a vector register (GR2VR) is zero. This optimization reduces the number of instructions and can improve performance. The change modifies the predicate matching and RTL generation to enable this combination.
In Details
This patch modifies config/riscv/predicates.md and config/riscv/riscv-v.cc to combine vec_duplicate + vmsgt.vv into vmsgt.vx when the GR2VR cost is zero. get_swapped_cmp_rtx_code in riscv-v.cc is updated to handle the RTL generation. This optimization is part of the RISC-V vector extension (RVV) and aims to improve code density and performance.
For Context
This commit introduces a compiler optimization for RISC-V processors using vector instructions. Vector instructions allow a single instruction to operate on multiple data elements simultaneously. The compiler can often combine multiple operations into a single vector instruction for improved performance. This change combines the operation of duplicating a value into a vector and then comparing the vector to another vector into a single instruction that compares a vector to a scalar value. The optimization is enabled only when the cost of moving data between different types of registers is zero, ensuring that the optimization is beneficial.