Improve slli+zext+andi sequence for RISC-V
Improved RISC-V code generation by optimizing the slli+zext+andi sequence into slli+srli.
The compiler now optimizes the sequence slli+zext+andi into slli+srli for RISC-V architectures. This optimization reduces the number of instructions needed for certain address calculations, potentially improving performance. A new test case was added to verify the optimization. The change was tested on both RISC-V 32-bit and 64-bit configurations.
In Details
This commit introduces a new define_insn_and_split pattern (slli_slli_uw) in config/riscv/bitmanip.md to optimize slli+zext+andi sequences into slli+srli on RISC-V. The existing plus+and+ashift splitter was converted to a define_insn_and_split to accommodate this new pattern. This change avoids regressions in zba-shadd.c. The commit also renames *slliuw to riscv_slli_uw. This targets the bitmanip extension, and interacts with the instruction selection and splitting phases.
For Context
Modern compilers transform high-level code into machine-specific instructions. This commit optimizes a particular sequence of instructions (slli+zext+andi) commonly used in address calculations on RISC-V processors. By replacing this sequence with a shorter one (slli+srli), the compiler can generate more efficient code, potentially leading to faster program execution. The changes are specific to RISC-V and leverage bit manipulation instructions for improved performance.