RISC-V: Utilize slliw instruction for left shifted signed bitfield extractions.
RISC-V code generation now uses `slliw` instruction to optimize left-shifted signed bitfield extractions, improving performance in specific scenarios.
This commit optimizes RISC-V code generation by using the slliw instruction for certain left-shifted signed bitfield extractions. This eliminates the need for separate sign extension instructions, resulting in more compact and efficient code. The optimization is specifically applied when extracting a sign-extended bitfield of size N, left-shifting it by M bits, and masking the result using AND, where N+M equals 32. This optimization improves performance in cases like the random number generator.
In Details
This commit introduces a new splitter in config/riscv/riscv.md called "masked shifted bitfield extraction". It recognizes the idiom of extracting a sign-extended bitfield of size N starting at bit 0, left-shifting it by M (where N+M == 32), and then masking the result with andi. This sequence is replaced with a single slliw instruction, improving code density. The optimization is triggered when a subsequent mask is applied using andi. The test case gcc.target/riscv/pr124955.c validates the new code generation pattern.
For Context
Modern processors often include specialized instructions to perform common operations more efficiently. This commit takes advantage of a specific instruction (slliw) on RISC-V processors to optimize a common code pattern: extracting a portion of a value (a bitfield), shifting it left, and then applying a mask. By using the slliw instruction, the compiler can perform these operations in fewer steps, leading to faster code execution.