AArch64 now supports vector concatenation for sub-64-bit types.
GCC now handles 2-element `vec_concats` with scalar operands on AArch64, and emits `vec_duplicate` when operands are identical.
This commit enhances the handling of 2-element vec_concats in aarch64_vector_init_fallback. It extends support to scalar operands and emits vec_duplicate instead of vec_concat when operands are identical, leading to better code generation. New combine instruction patterns back this change.
In Details
This patch introduces new instruction patterns (aarch64_combine_internal<mode>, aarch64_combine_internal_be<mode>, aarch64_combinez<mode>, aarch64_combinez_be<mode>) in aarch64-simd.md to support smaller vector and scalar modes in aarch64_vec_concat. A new mode iterator SSUB64 is also added within iterators.md. This refactoring enables more efficient handling of vector initialization.
For Context
Vector concatenation combines two or more vectors into a single, larger vector. This commit enhances GCC's ability to perform vector concatenation on AArch64 architectures, particularly for sub-64-bit data types. By allowing scalar operands and optimizing for identical operands, the compiler generates more efficient machine code, improving performance and reducing code size.