i386: Refines c86-4g fdiv scheduling model
GCC's i386 backend now refines the scheduling model for floating-point division to better reflect hardware behavior.
This commit refines the scheduling model for floating-point division on i386 architectures, specifically for the c86-4g model. It models a bounded part of the FPU pipe occupancy on a dedicated fdiv unit, improving the accuracy of instruction scheduling. The commit splits fpu0/fpu2 and fpu1/fpu3 into two paired automatons. It also corrects modelling omissions like a latency typo and adjustments to reservation units.
In Details
Commit r17-258 introduced separated c86-4g fdiv units to avoid automaton explosion. This patch refines it by modelling a bounded part of the FPU pipe occupancy. It splits fpu0/fpu2 and fpu1/fpu3 into two paired automatons. The scheduling model within the md files is updated, as well as various instruction latencies.
For Context
Instruction scheduling is the process of ordering instructions to maximize processor utilization and minimize stalls. This commit refines the scheduling model for floating-point division on i386 processors within GCC. By more accurately representing the hardware behavior, the compiler can generate more efficient code that executes faster.