RISC-V: Add Synopsys RHX-100 series pipeline description.
Adds pipeline description for Synopsys RHX-100 series processor to the RISC-V GCC backend.
This patch introduces the pipeline description for the Synopsys RHX-100 series processor to the RISC-V GCC backend. The RHX-100 features a 10-stage, dual-issue, in-order execution pipeline architecture. Due to instruction fusion, up to four instructions can be issued in a single cycle; it is modeled as four separate pipelines, and the issue_rate is set to four.
In Details
This commit adds a new target definition to the RISC-V backend for the Synopsys RHX-100 series processor. It defines the pipeline characteristics in arcv-rhx100.md and adds arcv_rhx100 to enum riscv_microarchitecture_type in riscv-opts.h. It also updates riscv-cores.def to include the new target. Knowledge of RISC-V target definition files and pipeline descriptions is needed; this target features a dual-issue pipeline with instruction fusion.
For Context
When compiling code for a specific processor, the compiler needs to understand the processor's internal architecture, including the pipeline (the sequence of stages an instruction goes through). This commit adds support for a new processor, the Synopsys RHX-100, to the RISC-V compiler. This allows the compiler to generate code that is optimized for the RHX-100's specific characteristics, potentially improving performance. This processor supports instruction fusion, allowing multiple instructions to execute in parallel.