AArch64: Add zeroing forms for predicated SVE integer unary operations
GCC now supports zeroing predication for SVE integer unary operations on AArch64, leveraging SVE2.2 and SME2.2 for optimized code generation.
This commit introduces support for zeroing predication in SVE integer unary operations (ABS, CLS, CLZ, CNT, CNOT, NEG, NOT, RBIT, SQABS, SQNEG, URECPE, URSRQTE) on AArch64 processors. Enabled by SVE2.2 and SME2.2, this change adds new alternatives to aarch64-sve.md and aarch64-sve2.md, emitting zeroing-predication forms when a const_vector of all zeroes acts as the merge operand. New tests have been added to validate the codegen for these zeroing variants.
In Details
This commit adds new alternatives to aarch64-sve.md and aarch64-sve2.md for zeroing predication of SVE integer unary operations, guarded by the sve2p2_or_sme2p2 condition. It covers instructions defined by the SVE_INT_UNARY and SVE2_U32_UNARY iterators, as well as the standalone CNOT pattern. The core idea is to emit zeroing-predication forms when the merge operand is a const_vector of all zeroes. Without familiarity with Arm's SVE and its predication features, toolchain developers outside of the AArch64 backend might miss the details.
For Context
This commit enhances GCC's support for Arm's Scalable Vector Extension (SVE) on AArch64 architectures. SVE enables CPUs to perform the same operation on multiple data elements simultaneously, increasing performance for suitable workloads. Predication is the conditional execution of an instruction based on a mask. Zeroing predication sets inactive vector lanes to zero. This patch adds support for new SVE2.2 and SME2.2 instructions that perform unary operations (like absolute value, negation, bitwise NOT) with zeroing predication. These instructions contribute to more efficient code generation when working with vector data.