AArch64: Fix SVE to SIMD lowering optimization.
Corrects an SVE to SIMD lowering optimization bug that generated invalid code on AArch64.
This patch fixes a bug in the SVE to SIMD lowering optimization for AArch64 architecture. The optimization, intended to convert SVE loads with known predicates into Adv. SIMD loads without predicates, was generating incorrect code due to scalar floating-point constants being created using vector broadcasting operations. The fix involves creating a full SVE vector of zeros and writing only the desired values using an INSR instruction, with patterns provided to optimize this process.
In Details
The optimization in g:210d06502f22964c7214586c54f8eb54a6965bfd has an implementation bug which makes it generate bogus code. Scalars FPR constants are created using vector broadcasting operations, which assumes scalars are accessed as scalars. The patch fixes this by creating a full SVE vector of 0s and writing only the values we want to set using an INSR.
For Context
AArch64 is the 64-bit ARM architecture. SVE (Scalable Vector Extension) is an ARM instruction set extension that allows for vector lengths to be scaled dynamically at runtime. SIMD (Single Instruction, Multiple Data) is a class of parallel processing where a single instruction operates on multiple data points simultaneously. This patch corrects an optimization that converts SVE instructions to SIMD instructions, ensuring correct code generation and preventing potential issues with floating-point constants.