Detect more czero opportunities on RISC-V
The RISC-V backend now recognizes more cases where `czero.eqz` can replace a sequence of `sgt`, `snez`, and `and` instructions.
The RISC-V backend now recognizes more cases where a sequence of sgt, snez, and and instructions can be replaced with the czero.eqz instruction. By generalizing existing patterns to accept both NE and EQ forms and handling commutative AND operations, the compiler can now generate more efficient code sequences when the Zicond extension is enabled. This change improves code generation efficiency in specific scenarios.
In Details
This commit modifies config/riscv/zicond.md to generalize patterns that identify opportunities to use the czero.eqz instruction. The original patterns only accepted NE forms and didn't account for the commutative property of the AND instruction. This change has a localized impact on RISC-V code generation when the Zicond extension is enabled.
For Context
This commit optimizes code generation for RISC-V processors that have the Zicond extension. The Zicond extension adds instructions that can conditionally set a register to zero based on the value of another register. By recognizing more opportunities to use these instructions, the compiler can generate more efficient code, potentially leading to faster execution times.