rs6000: Fix [su]mul<mode>3_highpart patterns to use RTL codes.
This commit fixes the `smul` and `umul` highpart patterns on rs6000 to properly generate widened multiply instructions.
This commit corrects the code generation for high-part multiplication on the rs6000 architecture. The previous implementation used incorrect shift-based patterns that did not match the semantics of the vmulhs<wd> and vmulhu<wd> instructions, which perform a widened multiplication and return the high part of the result. This patch replaces the incorrect patterns with the proper smul_highpart and umul_highpart RTL codes, ensuring correct code generation for high-part multiplication using Altivec registers.
In Details
The commit fixes incorrect smul<mode>3_highpart and umul<mode>3_highpart patterns in config/rs6000/vsx.md. The previous patterns incorrectly shifted both operands before multiplication, while the correct instructions (vmulhs<wd> and vmulhu<wd>) perform widened multiplication. The patch replaces shift-based patterns with smul_highpart and umul_highpart RTL codes, and updates the operand predicate to altivec_register_operand.
For Context
When a compiler generates code for a specific processor, it uses patterns to match operations in the source code to the available instructions of the processor. This commit fixes an issue on rs6000 series processors related to generating code for multiplication operations where you only want the high part of the result. The fix ensures that the compiler uses the correct instructions for these operations, resulting in correct and efficient code.