AArch64: Add zeroing forms for predicated SVE top FP conversions
The compiler now supports zeroing predication for several SVE FP conversion instructions, enabled under SVE2.2 or SME2.2.
The compiler now supports zeroing predication for several SVE FP conversion instructions, enabled under SVE2.2 or SME2.2. This change adds an alternative that emits a single zeroing-predication form of the instructions, as long as the sve2p2_or_sme2p2 condition holds. Narrowing conversions now use the new top_narrowing_convert SVE function base class, which injects a const_vector selector operand at expand time.
In Details
SVE2.2 and SME2.2 add zeroing predication to FP conversion instructions like BFCVTNT, FCVTLT, FCVTNT, and FCVTXNT. This commit modifies RTL patterns to emit the zeroing versions when the merge operand is a constant zero vector and sve2p2_or_sme2p2 is true. Narrowing conversions now use the top_narrowing_convert SVE function base class, which injects a const_vector selector operand at expand time to control the values of inactive lanes.
For Context
The Scalable Vector Extension (SVE) is an Arm architecture extension that allows vector instructions to operate on vectors of varying lengths. Predication is a feature that allows vector instructions to be conditionally executed based on a predicate vector. Zeroing predication is a form of predication where inactive lanes in the destination vector are set to zero. This commit adds support for zeroing predication to several SVE FP conversion instructions, enabled under SVE2.2 or SME2.2.