Improve RISC-V code generation for xor+xor+ior sequences
Improves RISC-V code generation by transforming `xor+xor+ior` sequences into more efficient `andn+xor` instructions.
This commit optimizes the code sequence generated for expressions like (a ^ b) ^ (a | c) on RISC-V. Instead of generating xor, or, xor instructions, the compiler now generates andn, xor when possible, which is more efficient. This optimization can lead to performance improvements for code that uses this type of expression.
In Details
This commit adds splitters to bitmanip.md in the RISC-V target to recognize and transform xor+xor+ior sequences into andn+xor. This transformation improves code generation by leveraging the andn instruction, which performs a bitwise AND with the complement of a register. The change targets a specific pattern identified in PR rtl-optimization/96692 and aims to improve the generated code's efficiency.
For Context
Compilers often perform optimizations by rearranging or replacing sequences of instructions with equivalent but faster sequences. This commit does this for a specific pattern of bitwise operations (XOR and OR) on the RISC-V architecture. By recognizing this pattern and using a specialized instruction (andn), the compiler can generate more efficient code, potentially leading to faster execution.