i386: Refactor AVX512 comparisons in machine description sse.md.
GCC's x86 backend now has a cleaner organization of AVX512 vector comparisons, avoiding nonsensical instruction combinations.
The x86 backend in GCC has been refactored to improve the organization of AVX512 vector comparisons. The previous organization led to the generation of potentially invalid instructions (e.g., integer comparisons specifying floating-point rounding modes). The new structure uses a more logical decomposition of patterns, ensuring that only valid instruction combinations are generated. This improves code quality by using the correct instructions.
In Details
This patch refactors the define_insns for vector comparisons on 512-bit vectors in sse.md. The original organization, based on mode iterators (V48H, VI12), resulted in the generation of instructions like avx512f_cmpv16si3_mask_round, which are semantically incorrect. The refactoring uses a decomposition into three patterns (VFH, VI1248 for signed and unsigned integers) to avoid these issues. The predicates are also simplified which means there are not changes to instruction emission other than removal of non-sensical patterns.
For Context
The x86 architecture supports Advanced Vector Extensions (AVX), which allow the processor to perform operations on multiple data elements simultaneously. AVX-512 is a further extension of this technology with 512-bit vectors, allowing for even greater parallelism. This commit reorganizes how GCC generates AVX-512 comparison instructions for the x86 architecture. The goal is to ensure that the compiler produces correct and efficient code when using these advanced vector instructions. The refactoring simplifies the internal representation and prevents the generation of nonsensical instruction combinations.