RISC-V: Remove blanket else in riscv_hard_regno_mode_ok
This commit removes unreachable code in `riscv_hard_regno_mode_ok` function in the RISC-V backend.
The riscv_hard_regno_mode_ok function in the RISC-V backend had an unnecessary else clause that was effectively unreachable. This commit removes the else clause, simplifying the code. This was found while investigating PR124439.
In Details
riscv_hard_regno_mode_ok determines whether a given register is valid for a specific mode. The removed else clause in config/riscv/riscv.cc always returned false, making it unreachable due to prior if conditions covering all possible valid register scenarios. The change has no functional impact since the code was unreachable.
For Context
The compiler's backend handles architecture-specific details during code generation. This commit modifies the RISC-V backend, which generates code for RISC-V processors. The change involves removing an unreachable else clause in the riscv_hard_regno_mode_ok function, which checks the validity of a register for a particular data type. Removing dead code improves readability.