rs6000: Add MPCCORE to TARGET_NO_LWSYNC to avoid illegal instructions.
GCC avoids generating `lwsync` instructions on MPC8xx PowerQUICC cores, which can cause crashes due to hardware limitations.
GCC now avoids emitting lwsync instructions for MPC8xx PowerQUICC processors. These older PowerPC cores don’t fully support the lwsync instruction and will fault if the instruction’s reserved bits aren’t zeroed. This change adds PROCESSOR_MPCCORE to the TARGET_NO_LWSYNC macro, which disables the generation of these instructions, preventing crashes on affected hardware. The fix was verified on MPC860 hardware after encountering an illegal instruction crash in libstdc++ atomics.
In Details
The rs6000 architecture in GCC requires specific handling for different PowerPC cores. The TARGET_NO_LWSYNC macro in config/rs6000/rs6000.h controls whether lwsync instructions are generated. Older MPC8xx cores don't fully support lwsync, so this commit adds PROCESSOR_MPCCORE to the macro to prevent their emission. This avoids illegal instruction faults, particularly when using libstdc++ atomics which may generate these instructions for memory ordering.
For Context
Modern processors use memory barriers to ensure that memory operations occur in the correct order. lwsync is a lightweight memory barrier instruction on PowerPC architectures. However, older PowerPC cores may not fully support lwsync and can crash if the compiler emits them. This commit ensures that GCC avoids generating problematic lwsync instructions when compiling for these older processors, preventing runtime errors.