RISC-V: Optimize shift+rotate sequences to simple shift instructions.
The RISC-V backend now optimizes specific shift and rotate sequences into a single shift instruction, improving code generation for bit manipulation.
The RISC-V backend now recognizes specific sequences of shifts and rotates with masking as a single shift instruction. This optimization applies when the shifts clear the upper bits and the rotate operates on the lower bits, with a consecutive run of set bits in the mask including bits 31..63. This reduces a 3-instruction sequence to a single slliw instruction, improving code density and potentially performance for bit manipulation operations. This addresses PR target/109038.
In Details
A new pattern rotate_with_masking_to_shift is added to bitmanip.md to recognize shift+rotate sequences that can be replaced with a simple shift instruction. This optimization targets code where shifts clear upper bits and a rotate operates on the lower bits under a specific mask. The condition mask is always going to be a consecutive run of on bits including bits 31..63 followed by The number of bits off in the mask must be 32 - rotate count ensures the transform is profitable. This is implemented as a define_insn.
For Context
In compiler optimization, instruction selection aims to find the best machine code sequence for a given operation. Rotate and shift instructions are common in bit manipulation. This commit optimizes a specific pattern on RISC-V where a shift followed by a rotate with masking can be combined into a single, more efficient shift instruction. This reduces code size and improves performance.