Store-merging pass considers bswap and fixes RISC-V build
The store-merging optimization in GCC now correctly handles byte-swap operations and resolves a build failure on RISC-V.
This commit enhances the store-merging optimization pass in GCC to account for widen_bswap_or_bitreverse operations, rather than relying on an expander for 32-bit byte swaps. This change resolves a build issue on the RISC-V architecture where the bswapsi2 expander caused a failure due to an incorrect FAIL condition. Now, the store-merging pass considers __builtin_bswap32 as cheap if a bswapdi2 expander is present, leading to more robust and correct code generation, especially for 64-bit targets.
In Details
The store-merging pass in gimple-ssa-store-merging.cc is an optimization that combines multiple small stores into a single wider store, improving efficiency. This commit refines its decision-making for targets with byte-swapping capabilities. Previously, a hack in riscv/bitmanip.md allowed the bswapsi2 expander to unconditionally FAIL, causing build breaks. The fix eliminates this hack and instead modifies maybe_optimize_vector_constructor and pass_optimize_bswap::execute to recognize widen_bswap_or_bitreverse (and thus __builtin_bswap32) as a cheap operation when a `bswapdi…
For Context
Compilers try to make your code run faster by reorganizing things. One such optimization is 'store-merging,' where the compiler combines several small writes to memory into one larger write. This commit improves how this optimization works, especially for operations that 'byte-swap' values (reverse the order of individual bytes within a number). Previously, a special setting for the RISC-V processor had an issue where it incorrectly failed when trying to deal with byte-swapping 32-bit numbers. This update fixes that by making the store-merging optimization smarter, allowing it to better understand and optimize code that uses byte-swapping functions like __builtin_bswap32, particularly on 64-bit systems. This means more efficient code and fixes a build error for RISC-V users.