Enable address tagging on 64-bit RISC-V with pointer masking.
GCC now supports hardware-assisted address sanitization (HWASan) on RISC-V 64-bit architectures with pointer masking.
This patch enables hardware-assisted address sanitization (HWASan) for RISC-V 64-bit targets that support the pointer masking extension. It implements TARGET_MEMTAG_CAN_TAG_ADDRESSES and TARGET_MEMTAG_TAG_BITSIZE to allow the use of -fsanitize=hwaddress. This improves memory safety by detecting memory errors at runtime, useful where software-based sanitizers are too slow.
In Details
This commit introduces TARGET_MEMTAG_CAN_TAG_ADDRESSES and TARGET_MEMTAG_TAG_BITSIZE in riscv.cc, leveraging the pointer masking extension for HWASan. The changes enable memory tagging, a hardware-assisted mechanism for detecting memory access errors. Toolchain devs outside the RISC-V backend should note the increasing adoption of HWASan and memory tagging across architectures.
For Context
Address sanitizers are tools that detect memory errors such as buffer overflows and use-after-free bugs during program execution. Hardware-assisted address sanitization (HWASan) uses hardware features of the CPU to speed up these checks, reducing the performance overhead compared to software-based sanitizers. This commit enables HWASan on RISC-V processors that have the pointer masking extension, which provides the necessary hardware support for memory tagging. Memory tagging associates a small tag with each memory location, and HWASan verifies that the tag matches when the memory is accessed. This helps catch memory errors that could lead to crashes or security vulnerabilities.