AArch64: Add zeroing forms for predicated SVE FP unary operations
The compiler now supports zeroing predication for SVE floating-point unary operations under SVE2.2 or SME2.2.
The compiler now supports zeroing predication for SVE floating-point unary operations under SVE2.2 or SME2.2. This change adds a new alternative to patterns in aarch64-sve.md and aarch64-sve2.md with Dz (the merge operand), enabled only if the sve2p2_or_sme2p2 condition holds, and emitting a single instruction with zeroing predication.
In Details
SVE2.2 and SME2.2 add zeroing predication to FP unary operations like FABS, FNEG, FRECPX, FRINT, FSQRT (SVE) and FLOGB (SVE2). This adds a new alternative to the patterns covered by SVE_COND_FP_UNARY and SVE2_COND_INT_UNARY_FP, enabled when sve2p2_or_sme2p2 is true.
For Context
The Scalable Vector Extension (SVE) is an Arm architecture extension that allows vector instructions to operate on vectors of varying lengths. Predication is a feature that allows vector instructions to be conditionally executed based on a predicate vector. Zeroing predication is a form of predication where inactive lanes in the destination vector are set to zero. This commit adds support for zeroing predication to SVE floating-point unary operations, enabled under SVE2.2 or SME2.2.