RISC-V canonical extension order now matches the latest ISA specification.
RISC-V extension canonical order is updated to align with the latest ISA specification, moving 'v' before 'p' and dropping 'n'.
The canonical order for RISC-V extensions has been updated to reflect recent adjustments in the RISC-V ISA manual. This change moves the ‘v’ (Vector) extension before ‘p’ (Packed-SIMD) and removes ‘n’ (User-level Interrupts) from the standard extension set. Although these extensions are not yet ratified, this update ensures GCC’s internal representation matches the evolving specification.
In Details
This commit synchronizes GCC's internal representation of RISC-V extension canonical order with recent changes in the RISC-V ISA manual. Specifically, it modifies riscv_supported_std_ext in common/config/riscv/riscv-common.cc and CANONICAL_ORDER in config/riscv/arch-canonicalize to place 'v' before 'p' and remove 'n'. This adjustment reflects the evolving, though not yet ratified, specification of these extensions.
For Context
The RISC-V instruction set architecture (ISA) is modular, meaning it can be extended with optional features like vector processing or bit manipulation. To keep track of these extensions consistently, there's a defined 'canonical order' in which they are listed. This commit updates GCC, the GNU Compiler Collection, to match the very latest official RISC-V ISA specification for this ordering. The change involves reordering 'v' (Vector extension) and 'p' (Packed-SIMD) and removing 'n' (User-level Interrupts), even though these extensions are not yet final. This ensures that GCC remains aligned with the most current understanding of the RISC-V architecture.