rs6000: Add missing ISA 3.0 atomic memory operation instructions
GCC now supports additional atomic memory operation instructions for the rs6000 architecture's ISA 3.0.
This commit adds support for missing atomic memory operation (AMO) instructions from the rs6000 architecture’s ISA 3.0. The new instructions include Compare and Swap Not Equal, Fetch and Increment Bounded, Fetch and Increment Equal, Fetch and Decrement Bounded, and Store Twin. These additions extend the capabilities for lock-free data structures and concurrent programming on PowerPC.
In Details
The changes to amo.h introduce new atomic memory operation functions corresponding to ISA 3.0 extensions. These include Compare and Swap Not Equal, Fetch and Increment Bounded, Fetch and Increment Equal, and Fetch and Decrement Bounded for load atomic operations, and Store Twin for store atomic operations. The added test cases (amo3.c through amo7.c) exercise these new instructions. Knowledge of PowerPC AMO instructions is needed to understand this patch.
For Context
Atomic memory operations are special instructions that allow multiple processors or threads to access and modify memory locations safely and without interfering with each other. This commit adds new atomic memory operation instructions for the rs6000 architecture (also known as PowerPC), specifically for the ISA 3.0 instruction set. These new instructions provide more ways to perform atomic operations, which are essential for building lock-free data structures and concurrent programs. This allows developers to write more efficient and reliable multithreaded applications on PowerPC systems.