Improve RISC-V Constant Synthesis for Some HImode Constants
The RISC-V backend now synthesizes HImode constants more efficiently, using `addi` instead of `li+xori` sequences in some cases, and allows CSE to derive const…
This commit improves the RISC-V backend’s handling of HImode (Half-Word Integer mode) constants. It changes the constant synthesis sequence to use addi (add immediate) instead of li+xori (load immediate + exclusive or immediate) instruction sequences in certain cases, resulting in smaller code size. The patch also adjusts the Common Subexpression Elimination (CSE) pass allowing it to derive new constants from existing ones using NOT/NEG operations, preventing a code quality regression.
In Details
The RISC-V backend's riscv_move_integer function is responsible for materializing integer constants. This commit modifies it to pass the post-promotion mode to riscv_build_integer, allowing for more efficient constant synthesis in HImode. Additionally, CSE is enhanced to utilize NEG/NOT for constant derivation, addressing a regression.
For Context
Compilers have to represent constant values in different ways depending on the target architecture and the size of the data. This commit optimizes how GCC represents small integer constants on RISC-V processors. This optimization reduces the number of instructions needed to load these constants, leading to slightly smaller and faster code.