RISC-V: Fix several bugs in macro fusion logic.
This patch fixes correctness and minor issues in the RISC-V macro fusion logic, including incorrect checks and typos.
Several correctness issues in the RISC-V macro fusion logic were fixed. An incorrect XINT access in RISCV_FUSE_AUIPC_LD was corrected to use SET_SRC (prev_set). The base register comparison in RISCV_FUSE_CACHE_ALIGNED_STD was corrected from != to ==. Redundant checks in RISCV_FUSE_B_ALUI and RISCV_FUSE_LDINDEXED were removed. A typo in a comment was fixed, and the dump output name for CACHE_ALIGNED_STD was corrected.
In Details
This commit addresses specific bugs within the riscv_macro_fusion_pair_p function in riscv-fusion.cc. These bugs involve incorrect operand access, wrong comparisons, and redundant checks within the instruction fusion logic. The fixes ensure correct behavior for AUIPC_LD, CACHE_ALIGNED_STD, B_ALUI, and LDINDEXED fusion cases. Tests are marked XFAIL because no upstream mtune currently enables these fusions.
For Context
Instruction fusion combines multiple instructions into a single instruction to improve performance. This commit fixes several bugs in the RISC-V macro fusion logic, ensuring the correct identification and fusion of instruction pairs. The fixes address issues such as incorrect operand access, wrong comparisons, and redundant checks, ensuring the fusion process behaves as expected.