Define duplication into sub-64-bit AdvSIMD vectors
GCC now supports duplicating elements into smaller Advanced SIMD vectors on AArch64, fixing an internal compiler error.
This commit introduces new instruction patterns to the AArch64 backend, enabling the definition of duplication operations into sub-64-bit Advanced SIMD (AdvSIMD) vectors. This resolves an Internal Compiler Error (ICE) that occurred when attempting to generate vec_duplicate expressions for smaller vector types during vector initialization fallbacks. By explicitly defining these patterns, GCC can now correctly handle vector splat operations for 16-bit and 32-bit destinations, improving the robustness of vector code generation on AArch64.
In Details
The Advanced SIMD (AdvSIMD) architecture in AArch64 provides instructions for single-instruction, multiple-data processing using vector registers. The vec_duplicate operation (or 'splat') involves replicating a single scalar value across all elements of a vector. This patch specifically addresses the case where the destination vector is sub-64-bit (e.g., 16-bit or 32-bit elements). The aarch64-simd.md file defines new insn patterns like *aarch64_simd_dup_subvector and related mode iterators (VSDUP, VCONS) to provide RTL support for these smaller vector duplications. This prevents…
For Context
Modern computer processors, like those found in mobile phones and servers (AArch64), often have special capabilities to process multiple pieces of data at once using 'vector instructions'. This is called SIMD (Single Instruction, Multiple Data). One common vector operation is 'duplication' or 'splatting', where you take a single value and copy it into every slot of a vector. This commit fixes a problem in GCC, the GNU Compiler Collection, that caused it to crash when trying to perform this duplication into smaller-sized vector types (like vectors holding 16-bit or 32-bit numbers). By adding specific instructions to the compiler that tell it how to handle these smaller vector duplications, GCC can now correctly generate code for these operations, making vector programming on AArch64 more robust and preventing internal errors.