AVR: Use hard-reg constraints in divmod instructions.
The AVR backend now uses hard-register constraints for division and modulo operations, simplifying the instruction patterns.
This change replaces explicit hard-register specifications with hard-register constraints in the instruction patterns for division and modulo operations. This simplifies the code and removes unnecessary splitting functions for these operations. No user-visible impact is expected.
In Details
The AVR backend's avr.md defines instruction patterns for division and modulo operations (divmod<mode>4, udivmod<mode>4). Previously, these patterns used explicit hard-register specifications. This commit replaces these with hard-register constraints, which should allow the compiler to select registers more flexibly. The division/modulo operation splitting functions are no longer needed.
For Context
Compilers translate high-level code into machine instructions through a series of steps. One step involves pattern matching, where the compiler identifies code sequences that correspond to specific machine instructions. This commit modifies how the AVR (a family of microcontrollers) compiler backend handles division and modulo operations during pattern matching. It replaces explicit register assignments with more flexible constraints, allowing the compiler to choose registers more efficiently.