x86 SSE: Improve vector increment/decrement on x86
The x86 backend now generates more efficient SSE code for incrementing and decrementing vectors by using subtraction instead of addition where appropriate.
The x86 backend now uses subtraction to add one (x + 1) and addition to subtract one (x - 1) from vectors when generating SSE code. This is more efficient because materializing the vector -1 is cheaper than materializing +1 with SSE instructions. This change avoids generating vpabsb instructions in some cases, resulting in shorter code sequences.
In Details
GCC's x86 backend's i386.md instruction patterns now use a plusminus iterator to generate more efficient SSE code for vector increments and decrements. Specifically, instead of always adding, the backend now sometimes inverts the operand and subtracts, or vice versa. This relies on the fact that materializing a vector of -1 is more efficient than a vector of +1 using SSE.
For Context
When compiling code, the compiler chooses the best sequence of machine instructions to perform the operations requested in the source code. For vector operations on x86 processors with SSE (Streaming SIMD Extensions), adding or subtracting vectors of ones is a common task. This commit optimizes how GCC generates SSE instructions for these vector increments and decrements, yielding faster code.